1. Field of the Invention
The present invention relates to transistor-transistor logic circuits (TTL circuits), and particularly to multiple-connected TTL circuits in which a plurality of TTL circuits are connected at their output terminals and each of the TTL circuits is operated selectively.
2. Description of the Prior Art
Prior art TTL circuits comprising a totem-pole-connected inverter transistor and an off-buffer transistor have been used. Two examples of such prior art TTL circuits are respectively illustrated in FIG. 1 and FIG. 4. The operating characteristics of the circuits of FIG. 1 and FIG. 4 are shown in FIG. 2 and FIG. 5, respectively.
In FIG. 1, an output terminal 6 is provided at the connecting point of a totem-pole-connected inverter transistor Q.sub.3 and an off-buffer transistor Q.sub.4. The collector of the input transistor Q.sub.1 is connected to the base of a phase-split transistor Q.sub.2, the collector and the emitter of which are connected to the base of an off-buffer transistor Q.sub.4 and the base of the inverter transistor Q.sub.3, respectively.
The operating characteristics of the circuit shown in FIG. 1 are illustrated in FIG. 2. When the input 1 exhibits a LOW level, the transistor Q.sub.3 is in an OFF state and the transistor Q.sub.4 is in an ON state so that a HIGH level is thereby obtained at the output 6. On the contrary, when the input 1 exhibits a HIGH level, the transistor Q.sub.3 is in an ON state and the transistor Q.sub.4 is in an OFF state so that a LOW level is thereby obtained at the output 6. Thus, the circuit of FIG. 1 operates as an inverter. However, in the case where the circuit of FIG. 1 is used in a multiplex form in which the output terminal of the circuit of FIG. 1 is connected to the output terminal of another TTL circuit, a problem is caused in that, when both the off-buffer transistor Q.sub.4 and the inverter transistor Q.sub.3 ' of another TTL circuit are in the ON state, the off-buffer transistor Q.sub.4 and the inverter transistor Q.sub.3 ' of another TTL circuit are in danger of being damaged due to a strong current flowing through these two transistors, as indicated in FIG. 3.
In FIG. 4, the output terminal 6 is provided at the connecting point of the totem-pole-connected inverter transistor Q.sub.3 and the off-buffer transistor Q.sub.4. The collector of the input transistor Q.sub.1 ' having two emitters is connected to the base of the phase-split transistor Q.sub.2, the collector and the emitter of which are connected to the base of the off-buffer transistor Q.sub.4 and the base of the inverter transistor Q.sub.3, respectively. One of the emitters of the input transistor Q.sub.1 ' is connected to a data input 1, and the other of the emitters of the input transistor Q.sub.1 ' is connected to a control input 2 through a buffer 3. The output of the buffer 3 is also connected to the base of the off-buffer transistor Q.sub.4 connected to the collector of the phase-split transistor Q.sub.2. The circuit shown in FIG. 4 is called a "tri-state" circuit or a "three-state" circuit.
The operating characteristics of the circuit of FIG. 4 are illustrated in FIG. 5. When the control input 2 exhibits a LOW level corresponding to the periods of t.sub.0 to t.sub.1 and t.sub.4 to t.sub.7, the phase-split transistor Q.sub.2 is not supplied with a base current regardless of the level of the data input 1, thus, the phase-split transistor Q.sub.2 is in an OFF state and, accordingly, the inverter transistor Q.sub.3 is in an OFF state. The off-buffer transistor Q.sub.4 is also in an OFF state since the diode 4 allows current conduction to occur, thus the potential of the connecting point of the collector of the transistor Q.sub.2 and the base of the transistor Q.sub.4 is caused to be maintained at a LOW level. Since both the inverter transistor Q.sub.3 and the off-buffer transistor Q.sub.4 are in the OFF state, the output 6 is in an OPEN state. This OPEN state is called "the third state".
When the control input 2 exhibits a HIGH level and the data input 1 exhibits a LOW level corresponding to the periods of t.sub.1 to t.sub.2 and t.sub.3 to t.sub.4, the phase-split transistor Q.sub.2 is in an OFF state. Accordingly, the inverter transistor Q.sub.3 is in an OFF state but the off-buffer transistor Q.sub.4 is in an ON state. Since the off-buffer transistor Q.sub.4 is in an ON state and the inverter transistor Q.sub.3 is in an OFF state, the output 6 exhibits a HIGH level. This HIGH level state is called "the first state".
When both the control input 2 and the data input 1 exhibit a HIGH level corresponding to the period of t.sub.2 to t.sub.3, the phase-split transistor Q.sub.2 is in an ON state. Accordingly, the inverter transistor Q.sub.3 is in an ON state but the off-buffer transistor Q.sub.4 is in an OFF state. Since the off-buffer transistor is in an OFF state and the inverter transistor is in an ON state, the output 6 exhibits a LOW level. This LOW level state is called "the second state".
In the case where a plurality of the type of TTL circuits of FIG. 4 are used and the output terminals of these TTL circuits are connected together to form a common output terminal, it does not occur that a large current is flowing through the series circuit of the inverter transistor Q.sub.3 and the off-buffer transistor Q.sub.4 as in the case of FIG. 1, since an off-buffer transistor, which can be in the ON state, of a TTL circuit is never connected to an inverter transistor Q.sub.3 in the ON state, as a result of keeping the TTL circuits which are not being used in the above-mentioned OPEN state (the third state). However, in the above-described case it is not always certain that a control input signal is supplied to only one TTL circuit, although the control input signal of a HIGH level should be supplied to only one TTL circuit. If the control signal is supplied once in an incorrect manner, a strong current will flow through the off-buffer transistor Q.sub.4 and the inverter transistor Q.sub.3, and thus, the off-buffer transistor Q.sub.4 and the inverter transistor Q.sub.3 will be in danger of being damaged due to the strong current flowing therethrough. Furthermore, the probability of an occurrence of the above-described incorrect supply of a control signal increases in accordance with the increase in the number of connected TTL circuits.
These prior art TTL circuits are disclosed in, for example, the Japanese publication "Electronics Digest" issue of October, 1971, on pages 2 and 3. The present invention was created to overcome the above-described problems of the prior art TTL circuits of FIG. 1 and FIG. 4.